FPGA Algorithms

Case Study

Basic Architecture

Significant cost reduction was required in a complex medical imaging system. A spurious comment about putting the system into an FPGA was followed up with a few ranging calculations and then a serious investigation.

Most of the processing requirement resided in a few core algorithms; these needed access to raw data and coefficients, and needed to supply the output data in a suitable format. The first significant task was analysis of these core agorithms; this was followed by evaluation of the possible architectures that could be employed to implement them.

The architectures were evaluated by consideration of extreme possibilities; examples are the inclusion of various depths of buffering before and after the main algorithm. Examining the consequences of these gradually established the ground rules for possible and practical archetectures. Through this it was discovered that by setting certain depths of buffer, and altering the algorithm’s processing sequence, it was possible to implement it in the available technology. One of the consequences was a move from floating to fixed point operations.

Future Proofing

Consideration was also given to the nature of algorithms being used: Would they be changing often? This would make them impractical for FPGA implementation. It was demonstrated that the core algorithm was highly adaptable through changes in coefficients and parameters. However, as this was a move from algorithms implemented in software to firmware, great care was taken in establishing an in-service upgrade path for all of the algorithms. The design specification was then expanded to include adequate margins for unknown future possibilities.


With the potentially dramatic cost reduction established for the dominant process, the same approach was extended to other significant system processes. This resulted in further benefits for the system as a whole, especially in cost and size reduction.

During this phase, the economic case for moving ahead with the development was made. The project went ahead despite tremendous organisational changes. A team of FPGA engineers were contracted and managed for the term of the project. It eventually led to a success product.

Key to coordination and eventual technology transfer was a set of documented specifications; these ensured orderly implementation of each FPGA and related subsystem.

Testability was designed in at a very early stage, easing the development and verification path. A MATLAB model of the key algorithms was commissioned; this allowed verification of the specification prior to implementation in FPGA’s, as well as testing and debugging FPGA simulations and finally the same with physical implementation.